1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? power supply monitor resets processor when v cc power loss occurs and holds processor in reset during v cc ramp -up ? battery monitor checks remaining capacity daily ? read and write access times of 70ns ? unlimited write cycle endurance ? typical standby current 50 a ? upgrade for 32k x 8 sram, eeprom or flash ? lithium battery is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1330y) or optional 5% v cc operating range (ds1330ab) ? optional industri al temperature range of -40 c to +85 c, designated ind ? powercap module (pcm) package - directly surface - mountable module - replaceable snap - on powercap provides lithium backup battery - standardized pinout for all nonvolatile (nv) sram products - d etachment feature on powercap allows easy removal using a regular screwdriver pin assignment pin description a0 C a14 - a ddress inputs dq0 C dq7 - data in/data out ce - chip enable we - write enable oe - output enable rst - reset output bw - battery warning v cc - power (+5v) gnd - ground nc - no connect description the ds1330 256k nv srams are 262,144 - bit, fully static, nv srams organized as 32,768 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium ener gy source is automatically switched on and write protection is unconditionall y enabled to prevent data corruption. additionally, the ds1330 devices ha ve dedicated circuitry for monitoring the status of v cc and the status of the internal lithium battery. ds1330 devices in the powercap module package are directly surface mountable and are normally paired with a ds9034pc powercap to form a complete nv sram module. the devices can be used in place of 32k x 8 sram, eeprom, or flash compone nts. ds1330y/ab 256k nonvolatile sram with battery monitor 1 bw 2 3 nc nc rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gn d 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 nc gnd v bat 34- pin powercap module (pcm) ( uses ds9034pc + or ds9034pci+ powercap ) www.maxim - ic. com 19 - 5593 ; rev 10/10 downloaded from: http:///
ds1330y/ab 2 of 1 0 read mode the ds1330 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 15 addres s inputs (a 0 C a 14 ) defines which of the 32,768 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (a ccess time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satis fied, then data access must be measured from the later occurring sign al ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1330 devices execute a write cycle whenever the we and ce signals are in the active (low) state after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the outpu t drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1330ab provides full - functional capability for v cc greater th an 4.75v and write protects by 4.5v. the ds1330y provides full - functional capability for v cc greater than 4.5v and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nv srams constantly monitor v cc . should the supply voltage decay, the nv srams automatically writ e protect themselves, all inputs become dont care, and all outp uts become high - impedance. as v cc falls below approximately 2.7v, the power switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 2.7v, the power switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal r am operation can resume after v cc exceeds 4.75v for the ds1330ab and 4.5v for the ds1330y. system power monitoring ds1330 devices have the ability to monitor the external v cc power supply. when an out - of - tolerance power supply condition is detected, the nv srams warn a processor - based system of impending pow er failure by asserting rst . on power -up, rst is held active for 200ms nominal to prevent system operation during power - on transients and to allow t rec to elapse. rst has an open drain output drive r. battery monitoring the ds1330 devices automatically perform periodic battery voltage mo nitoring on a 24 - hour time interval. such monitoring begins within t rec after v cc rises above v tp and is suspended when power failure occurs. after each 24 - hour pe riod has elapsed, the battery is connected to an internal 1m ? test resistor for one second. during this one second, if battery voltage falls below th e battery voltage trip point (2.6v), the battery warning output bw is asserted. once asserted, bw remains active until the module is replaced. the battery is still retested after each v cc power - up, however, even if bw is active. if the battery voltage is found to be higher than 2.6v during such testing, bw is de - asserted and regular 24 - hour testing resumes. bw has an open drain output driver. downloaded from: http:///
ds1330y/ab 3 of 1 0 packages the 34 - pin powercap module integrates sram memory and nv control along with contacts for connection to the lithium battery in the ds9034pc powercap. the powercap module p ackage design allows a ds1330 pcm device to be surface mounted without subjecting its l ithium backup battery to destructive high - temperature reflow soldering. after a ds1330 pcm is reflow soldered, a ds9034pc is snapped on top of the pcm to form a complete nv sram module. the ds9034p c is keyed to prevent improper attachment. ds1330 powercap modules and ds9034pc powercaps are orde red separately and shipped in separate containers. see the ds 9034pc data sheet for further information. downloaded from: http:///
ds1330y/ab 4 of 1 0 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +6.0v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature range -55 c to + 125 c lead temperature (soldering, 10 s ) +260c soldering temperature (reflow) +260c this is a stress rating only and functional operation of the device at these or any other condit ions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating con ditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1330ab power supply voltage v cc 4.75 5.0 5.25 v ds1330y power supply vo ltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.8 v dc electrical characteristics (v cc = 5v 5% for ds1330ab) (t a : see note 10) (v cc = 5v 10% for ds1330y) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma 14 output current @ 0.4v i ol 2.0 ma 14 standby current ce =2.2v i ccs1 200 600 a standby current ce =v cc -0.5v i ccs2 50 150 a operating current i cco1 85 ma writ e protection voltage (ds1330ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1330y) v tp 4.25 4.37 4.5 v downloaded from: http:///
ds1330y/ab 5 of 1 0 capacitance (t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf ac electrical characteristics (v cc = 5v 5% for ds1330ab) (t a : see note 10) (v cc = 5v 10% for ds1330y) parameter symbol ds1330ab-70 ds1330y-70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 45 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 12 ns 12 13 output high z from we t odw 25 ns 5 output active from we t oew 5 ns 5 data setup tim e t ds 30 ns 4 data hold time t dh1 t dh2 0 7 ns 12 13 read cycle see note 1 downloaded from: http:///
ds1330y/ab 6 of 1 0 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 13 downloaded from: http:///
ds1330y/ab 7 of 1 0 power - down/power - up condition batt ery warning detection downloaded from: http:///
ds1330y/ab 8 of 1 0 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc fail detect to rst active t rpd 15 s 14 v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write pro tection t rec 125 ms v cc valid to rst inactive t rpu 150 200 350 ms 14 v cc valid to bw valid t bpu 1 s 14 battery warning timing (t a : see note 10) paramete r symbol min typ max units notes battery test cycle t btc 24 hr battery test pulse width t btpw 1 s battery test to bw active t bw 1 s (t a = + 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. note s: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transiti on, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high - impedance stat e during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period . downloaded from: http:///
ds1330y/ab 9 of 1 0 9. each ds1330 has a built - in switch that disconnects the lithium source until the user first app lies v cc . the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this parameter is assured by component selection, process control, and design. it is not measured directly during production testing. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0 c to +70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. rst and bw are open drain outputs and cannot source current. external pull - up resistors should be connected to these pins for proper operation. both pins will sink 10 ma. 15. ds1330 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0 C 3.0v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance pin - package ds1330abp-70+ 0c to +70c 5v 5% 34 pc ap * ds1330abp- 70ind+ - 40c to +85c 5v 5% 34 pcap * ds1330yp-70+ 0c to +70c 5v 10% 34 pcap * ds1330yp- 70ind+ - 40c to + 85c 5v 10% 34 pcap * + denotes a lead (pb) - free/rohs - compliant p ackage . * ds9034pc + or ds9034pci + (powercap) required. must be ordered separately. package information for the latest package outline information and land patterns, go to www.maxim -ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may sho w a different suffix character, but the drawing pertains to the package regard less of rohs status. package type package code outline no. land pattern no. 34 pcap pc2+4 21-0246 downloaded from: http:///
ds1330y/ab 10 of 1 0 r evision history revision date description pages changed 10/10 updated the storage , lead, and soldering information in the absolute maximum ratings section, removed the unused ac timing specs in the ac electrical characteristics table, updated the orderin g information table, replaced the package outline drawing with the package information table 1, 4, 5, 9 downloaded from: http:///
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